1. Field of the Invention
The invention relates in general to a high-speed serial linking device, and more particularly to a high-speed serial linking device with de-emphasis function and the method thereof.
2. Description of the Related Art
As higher and higher data transmission speed in computer is requested, existing parallel transmission architectures, PCI architecture for instance, become insufficient to satisfy consumers' demand. Parallel link architectures use plural linking lines and further synchronize the clock pulses of these linking lines. It is very difficult to synchronize the clock pulses of plural linking lines under high-speed data transmission.
The current practice of high-speed data transmission uses serial link transmission such as PCI express architecture whose data rate can be as high as 2.5 GHz or over. But, such high frequency signals will suffer a large amount of signal loss during transmission on the circuit board. Normally, de-emphasis technology is used to reduce high-frequency signal loss.
FIG. 1 is the diagram showing the wave form of a high-frequency serial link signal transmission using de-emphasis technology. High-frequency signals can be transmitted via a transmission differential pair TDP and TDN. When two consecutive bits are identical, high-frequency signal loss becomes significant. Hence de-emphasis technology is used to reduce the voltage swings of the second bit and of onward bits in a string of identical bits so as to reduce high-frequency signal loss. Take TDN signal for example. The bit values of TDN signal are shown at the bottom of FIG. 1 wherein two consecutive ‘0’s occur at D3 and D4 while three consecutive ‘0’s occur at D6, D7 and D8. With the occurrence of consecutively repeated bits, the voltage swings of D4, D7 and D8, the second and onward bits in a string of identical bits, are reduced so as to reduce high-frequency signal loss. The above application still holds true when consecutive ‘1’s occur and is not repeated here.
The above de-emphasis method first of all checks the occurrence of consecutively repeated bits: if found, these consecutively repeated bits are modulated to reduce voltage swings. However, since the data rate of high-frequency signals is getting faster and faster, the bit time becomes shorter and shorter. For example, one bit time unit under PCI express architecture is only 400 ps. It is extremely difficult to execute the inspection circuit and modulation circuit of de-emphasis technology within such a short bit time.